The present invention relates generally to memory devices, and more specifically to a read only memory (ROM) embedded in a dynamic random access memory (DRAM).
Memory devices are typically provided as internal storage areas in a computer or other electronic device requiring memory, such as cellular telephones, handhelds, and the like. There are several different types of memory. One type of memory is random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents.
A dynamic random access memory (DRAM) is made up of memory cells. Each cell of a modern DRAM includes a transistor and a capacitor, where the capacitor holds the value of each cell, namely a xe2x80x9c1xe2x80x9d or a xe2x80x9c0,xe2x80x9d as a charge on the capacitor. Because the charge on a capacitor gradually leaks away, DRAM capacitors must be refreshed on a regular basis. A memory device incorporating a DRAM memory includes logic to refresh (recharge) the capacitors of the cells periodically or the information will be lost. Reading the stored data in a cell and then writing the data back into the cell at a predefined voltage level refreshes a cell. The required refreshing operation is what makes DRAM memory dynamic rather than static.
The transistor of a DRAM cell is a switch to let control circuitry for the RAM either read the capacitor value or to change its state. The transistor is controlled by a row line coupled to its gate connection. In a read operation, the access device is activated and sense amplifiers coupled to bit lines (column) determine the level of charge provided to or dumped onto the digit lines from the memory cell, and reads the charge out as either a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d depending upon the level of charge in the capacitor. In a write operation, the sense amplifier is over-powered and the memory cell capacitor is charged to an appropriate level.
Referring to FIG. 1, a DRAM memory cell 200 is illustrated. The cell 200 is illustrated as having a capacitor 202 and an access transistor 204. The capacitor 202 is used to store a charge. The charge represents a bit of information. The access transistor 204 acts as a switch for the capacitor 202. That is, the access transistor 204 controls when a charge is placed on the capacitor 202, and when a charge is discharged from the capacitor 202. A word line is coupled to a control gate of the access transistor 204. When a cell is read, the word line activates the control gate of the transistor 204. Once this happens, any charge (or lack of charge) stored on the capacitor 202 is shared with a conductive digit line coupled to the drain of the access transistor 204. This charge is then detected in the digit line by a sense amplifier and then processed to determine the bit state of the cell 200. Tiling a selected quantity of cells together, such that the cells along a given digit line do not share a common word line and the cells along a common word line do not share a common digit line, forms a memory array. A typical memory array contains thousands or millions of cells.
After a cell has been accessed, sensing occurs. Sensing is necessary to properly read the data and refresh the cells. A simplified illustration of a typical sense amplifier is shown in FIG. 2. As FIG. 2 illustrates, the sense amplifier includes a Psense-amp and a Nsense-amp. The Psense-amp includes a pMOS pair of transistors, and the Nsense-amp includes an nMOS pair of transistors. Also labeled in FIG. 2 is node ACT (for ACTive pull up) on the Psense-amp, and node NLAT* (Nsense-amp LATch) on the Nsense-amp. ACT and NLAT provide power and ground. Initially, NLAT* is biased to Vcc/2 and Act is biased to Vss or signal ground. Since, the digit line pair D0 and D0* are both at Vcc/2, the nMOS pair of transistors and the pMOS pair of transistors are turned off. When a cell is accessed that is coupled to either D0 or D0*, a voltage difference occurs between D0 and D0*. While one of the digit lines contains charge from the cell access, the other digit line serves as a reference for the sensing operation.
After the cell is accessed the sense amplifiers are generally fired sequentially, the Nsense-amp first, followed by the Psense-amp. The Nsense-amp is fired by pulling NLAT* toward ground. As the voltage difference between NLAT* and the digit lines approaches Vth, the nMOS transistor whose gate is connected to the higher voltage digit line begins to conduct. This conduction causes the low-voltage digit line to be discharged toward the NLAT* voltage. Ultimately, NLAT* will reach ground, and the digit line will be brought to ground potential. Sometime after the Nsense-amp fires, the Psense-amp is activated by bring the ACT toward Vcc. The Psense-amp operates in a complementary fashion to the Nsense-amp. With the low-voltage digit line approaching ground, there is a strong signal to drive the appropriate pMOS transistor into conduction. This conduction charges the high-voltage digit line toward ACT, ultimately reaching Vcc. The capacitor of the cell being read is refreshed during the sensing operation. This is accomplished by keeping the access transistor of the cell on when the Psense-amp is activated. The charge the capacitor of the cell had prior to accessing the cell is fully restored. That is, the charge will be restored to Vcc for a 1 bit and GND for a 0 bit.
One technique for physically programming ROM embedded cells in a DRAM array is described in U.S. Pat. No. 6,134,137 issued Oct. 17, 2000 entitled xe2x80x9cROM-Embedded-DRAMxe2x80x9d, incorporated herein by reference. U.S. Pat. No. 6,134,137 teaches that slight modifications in fabrication masks allow DRAM cells to be hard programmed to Vcc or Vss by shorting the cell to word lines. The memory reads the ROM cells in a manner that is identical to reading the DRAM cells.
It would be desirable to improve the read and write efficiency and to simplify the read and write process for a ROM embedded DRAM.
In one embodiment, a ROM embedded DRAM includes a memory array having a first portion of ROM cells and a second portion of DRAM cells. The ROM cells include a number of DRAM cells hard shorted to one ROM bit polarity, and the remaining DRAM cells programmable to an opposite ROM bit polarity.
In another embodiment, a ROM embedded DRAM includes a DRAM array having a first subarray containing bits identified as ROM (or nonvolatile) bits and a second subarray having DRAM (or volatile) bits. In the ROM bit section of the ROM embedded DRAM, ROM bits of a first polarity are hard shorted to a first ROM bit polarity, and ROM bits of a second, complementary polarity remain as DRAM cells within the ROM bit section, and are programmed as DRAM bits to the second polarity.
In yet another embodiment, a method of programming a ROM section of a ROM embedded DRAM includes hard programming all non-volatile cells of one polarity to their values, and blanket programming all volatile cells of the ROM section to the opposite polarity.
In yet another embodiment, a dynamic read only memory (DROM) includes first memory cells programmed in a non-volatile manner to a first data state, and second memory cells dynamically programmed to a second data state, wherein the second memory cells comprise capacitors.
Other embodiments are described and claimed.